1. Field of the Invention
This invention relates to flat-cell mask ROM's and more particularly to a process for manufacture thereof.
2. Description of Related Art
The current flat-cell (buried bit line) MASK ROM architecture employs a select transistor for every 16 or 32 bits to divide the memory array into a number of blocks as shown in FIG. 1. In FIG. 1, buried bit lines 9, 10, and 11, etc. extend vertically (on the page) and polysilicon word lines 12 and 13 extend horizontally (on the page), with the word lines 12 and 13 having with a rectilinear relationship to the bit lines. A polysilicon select word line 20 is provided for selecting transistors. A pair of buried N+ regions 16 are juxtaposed with the select word line 20. Region 16 and buried bit lines 9, 10, 11 form the source/drain for the selecting transistor. Metal lines will make contact to the contact opening in the region 16. Located centrally in the regions 16 are a pair of contacts 18. The separation of the array blocks can enhance the sensing speed. More importantly the use of select transistors allows the relaxation of metal pitch. (Two buried bit lines require one metal line.)
As shown in FIG. 2 which shows another aspect of the prior art, because a phenomenon known as "corner rounding" at the ends of lines 10 and 11 where they pass beneath the polysilicon select word line 20 resulting from use of photolithography, the polysilicon select word line 20 to buried N+ region 24 alignment process becomes very critical to reduce cell current being sensed through the select transistor. The problem of low yield has been found to be related to low cell current.
An object of this invention is to provide an improved process in which the mask ROM can be manufactured with no misalignment/corner rounding effect of the kind described above caused by use of the conventional process.